The present invention relates to semiconductor devices functioning as heterojunction bipolar transistors including epitaxial base layers, and methods for fabricating the same.
Operation speed of silicon bipolar transistors has been increased through use of progress in microfabrication and self-alignment technique. In order to further increase the operation speed, research and development of bipolar transistors with heterojunction (heterojunction bipolar transistors) has been actively conducted. More specifically, in recent years, active attempts have been made to use SiGe mixed crystalline semiconductors (i.e., SiGe heterojunction bipolar transistors which will be herein referred to as xe2x80x9cSiGe-HBTsxe2x80x9d) as base layers.
FIGS. 14A through 14F are cross-sectional views illustrating a typical method for fabricating an SiGe-HBT using a known selective SiGe epitaxial growth technique.
First, in a process step shown in FIG. 14A, an N+ impurity layer 102 is formed in an upper part of a p-type silicon substrate 101 by ion implantation, and then an Nxe2x88x92 epitaxial layer 103 is formed thereon. Thereafter, an isolation oxide film 104 is formed using a trench formation technique and an oxide film embedding technique.
Next, in a process step shown in FIG. 14B, an oxide film 105 and a nitride film 106 are deposited by CVD in this order over the substrate, and then using a photolithography technique and an etching technique, a collector opening 115 (i.e. a region where epitaxial growth is to be performed and which will be herein also referred to as a xe2x80x9cepitaxial growth regionxe2x80x9d) is formed in the nitride film 106. Furthermore, the oxide film 105 is wet-etched to remove an exposed part thereof corresponding to the collector opening 115.
Next, using molecular beam epitaxy (MBE), ultra-high vacuum chemical vapor deposition (UHV-CVD) or low-pressure chemical vapor deposition (LP-CVD), an SiGe layer 107 including an Si cap layer, an SiGe spacer layer and a graded SiGe layer is epitaxially grown in an epitaxial growth region corresponding to the collector opening 115. At this point, use of the selective SiGe epitaxial growth technology can prevent deposition of a polycrystalline layer on the nitride film 106.
Next, in a process step shown in FIG. 14C, an oxide film 109 is deposited over the substrate and then is partially removed through a photolithography technique and an etching technique so that part of the oxide film 109 is left on the center portion of the Si/Ge layer 107.
Thereafter, in a process step shown in FIG. 14D, a polysilicon film 110 that is to serve as a base lead-electrode is deposited over the substrate, and then ions of boron as an impurity are implanted into the polysilicon film 110. Thereafter, an oxide film 111 is deposited on the polysilicon film 110. Then, an emitter opening 116 is formed in the oxide film 111 and the polysilicon film 110 through a photolithography technique and an etching technique.
Next, in a process step shown in FIG. 14E, an oxide film and a nitride film are deposited over the substrate, and then anisotropic dry etching is performed to form an oxide film sidewall 118 and a nitride film sidewall 112 on each side wall of a lamination of the oxide film 111 and the polysilicon film 110. Furthermore, the oxide film 109 is wet-etched to remove an exposed part thereof corresponding to the emitter opening 116.
Thereafter, in a process step shown in FIG. 14F, an n-type polysilicon film that is to serve as an emitter electrode is deposited over the substrate. Subsequently, using a photolithography technique and an etching technique, the polysilicon film is patterned and an emitter polysilicon electrode 113 is formed. Thereafter, thermal annealing such as RTA is performed to diffuse an n-type impurity from the emitter polysilicon electrode 113 into the Si cap layer in the Si/SiGe layer 107 such that an Si emitter layer is formed on an SiGe base layer. In this manner, an emitter and base junction is formed.
By following the process steps described above, an SiGe-HBT having an Sixe2x80x94SiGe heterojunction is formed.
FIG. 15 shows a schematic cross-section of an Si/SiGe layer 107 of an SiGe-HBT taken along the line XVxe2x80x94XV shown in FIG. 14F and the profile of the Ge content of the Si/SiGe layer 107 in the depth direction. As shown in FIG. 15, the Si/SiGe layer 107 includes a non-doped SiGe spacer layer 107a located directly on the Nxe2x88x92 epitaxial layer 103, a graded SiGe layer 107b provided on the SiGe spacer layer 107a, and an Si cap layer 107c. The upper portion of the Si cap layer 107c is doped with an n-type impurity by diffusion to serve as an emitter layer while the lower portion of the cap layer 107c serves as part of a base layer. In the graded SiGe layer 107b, the Ge content decreases gradually in the direction heading from the SiGe spacer layer 107a to the Si cap layer 107c. 
FIG. 16 is a timing chart showing a sequence of standard process steps of known SiGe epitaxial growth. Epitaxial growth of an SiGe film using UHV-CVD will be described herein. However, an epitaxial film can be also grown in a similar manner using LP-CVD or MBE.
As shown in FIG. 16, a wafer is loaded into a reaction chamber at a timing t100. Then, the temperature of the wafer is increased to a high temperature ranging from about 650xc2x0 C. to 800xc2x0 C. for a period from a timing t101 to a timing t102. Then, annealing (pre-cleaning) is performed for a period from the timing t102 to a timing t103 (e.g., for about 2 to 20 min.). Specifically, a natural oxide film formed on the upper surface of a semiconductor substrate is reacted with silicon in the substrate so that SiO having a high vapor pressure is removed (sublimated) thereon. As a result, a clean Si surface is exposed in a region where epitaxial growth is intended to be performed. The reaction is represented by the following formula:
SiO2+Sixe2x86x922SiO↑
Next, for a period from the timing t103 to a timing t104, the wafer temperature is reduced to a growth temperature ranging from about 500xc2x0 C. to 650xc2x0 C., and then the wafer is held to stand for a period from the timing t104 to a timing t105 until the temperature distribution of the wafer surface is uniformalized. At the timing t105, each layer is started to be grown by introducing source gases such as disilane, monogermane and diboran into a process chamber at respective predetermined flow rates. In this case, for example, an SiGe spacer layer 107a is formed by supplying disilane (Si2H6) and monogerman (GeH4) to the upper surface of the wafer at constant flow rates, respectively, for a period from the timing t105 to a timing t106. For the period from a timing t106 to a timing t107, a graded SiGe layer 107b is grown by reducing the flow rate of monogerman gradually under the condition that the flow rates of disilane and diboran (B2H6) are kept constant and thereby grading the Ge content. Furthermore, an Si cap layer 107c is grown by supplying disilane to the upper surface of the wafer at a constant flow rate for a predetermined period of time from the timing t107.
Meanwhile, in recent years, non-selective epitaxial SiGe growth technique have been regarded as promising techniques that allow achievement of high-performance SiGe-HBTs. In the non-selective SiGe epitaxial growth techniques, as disclosed in Japanese Unexamined Patent Publication No. 5-175222 and Japanese Unexamined Patent Publication No. 6-69434, an SiGe epitaxial film is grown on an silicon layer while an SiGe polycrystalline film is grown on an insulating film, such as an oxide film and a nitride film, located around the silicon layer. When such a non-selective epitaxial growth technique is applied to the process steps shown in FIGS. 14A through 14F, a polycrystalline Si/SiGe film is formed between the nitride film 106 and the polysilicon film 110 and thus the polysilicon film 110 and the polycrystalline Si/SiGe film serve as a base lead-electrode, resulting in reduction in resistance of the base lead-electrode.
Such non-selective SiGe epitaxial growth techniques for use in fabricating SiGe-HBTs are regarded as promising techniques that allow improvement of electric properties of transistors and stable transistor production from the following points.
(1) A polycrystalline SiGe film is formed on the insulating film while a single crystalline SiGe film is epitaxially grown over a substrate. In general, the polycrystalline SiGe film has a lower specific resistance than a polycrystalline Si film. More specifically, in an SiGe-HBT, an SiGe polycrystalline film heavily doped with B can be used as part of a base lead-electrode of the bipolar transistor. Accordingly, the base resistance can be further reduced.
(2) In a BiCMOS process, a polycrystalline SiGe film can be used not only as part of a base lead-electrode of a bipolar transistor but also as a gate electrode of an MOS transistor. Thus, the gate resistance and the number of process steps can be reduced.
(3) When a selective SiGe epitaxial growth technique is used, growth selectivity is reduced due to small changes in growth conditions, thus easily causing the phenomenon that polycrystals are formed in the form of islands on an insulating film or like phenomena. In other words, a process margin is small, thus easily causing abnormal states in process steps. In contrast, when a non-selective epitaxial growth technique is used, a polycrystalline film is formed on the insulating film. Therefore such abnormal states as caused by epitaxial growth is said hardly appear.
As have been described, although non-selective SiGe epitaxial growth techniques are promising techniques in terms of improving electric properties of SiGe-HBTs, the following problems caused by the techniques have been found.
(1) Unlike epitaxial growth on an silicon layer, epitaxial growth does not start on an insulating film such as an oxide film and a nitride film until the density of growth nuclei (critical nuclei) larger than a certain grain size that have been formed thereon reaches or exceeds a certain level. Accordingly, in the case of epitaxial growth on the insulating layer, a time lag (latent time) occurs between the start of film growth and the start of supply of a process gas.
(2) As the Ge content of SiGe is increased, non-selectivity is reduced (that is, the latent time becomes longer).
Due to the problem (1), even if the SiGe polycrystalline film is intended to be used as part of the base lead-electrode, a polycrystalline film having a sufficient thickness can not be formed on the insulating layer during epitaxial growth of an Si/SiGe layer. This may result in failure of reduction in base resistance. Moreover, the problem (2) makes it difficult to simultaneously achieve both of reduction in base resistance by non-selective SiGe epitaxial growth and improvement of high-frequency properties by the increase in the Ge content.
FIG. 17A is an SEM photo showing a cross-section of an SiGe epitaxial film with the structure of the known semiconductor device formed by non-selective epitaxial growth. In a sample used for analysis of the cross-sectional structure, however, the formation of the oxide film 105 and the nitride film 106 as shown in FIG. 14B were omitted. The photo of FIG. 17A was taken using the sample including a 40 nm thick SiGe spacer layer 107a with a 15% Ge content, a 40 nm thick graded SiGe layer 107b in which the Ge content is graded from 15% to 0% and a 30 nm thick Si cap layer 107c. As shown in FIG. 17A, the epitaxially grown Si/SiGe layer 107 exists on the Nxe2x88x92 collector layer 103, whereas on the isolation oxide film 104, only island-shaped polycrystals but no polycrystalline film is formed.
FIG. 18 is an illustration schematically showing the relation between the thickness of a grown film and the radiation time during which a source gas is supplied for the SiGe epitaxial film, the Si epitaxial film, and the polycrystalline Si and SiGe films formed on the insulating film, for the purpose of further describing the causes of the problems (1) and (2). The following is what can be seen from FIG. 18.
In general, an SiGe epitaxial film has a greater growth rate than an Si epitaxial film. The growth rate of the SiGe epitaxial film increases as the Ge content of SiGe increases.
In forming a polycrystalline Si film or a polycrystalline SiGe film on an insulating film, formation of growth nuclei of SiGe resulting from decomposition of a source gas conflicts with the elimination reaction of the resultant SiGe from the surface of the insulating film, thus resulting in a time lag (latent time) from the start of supply of the source gas. In other words, dangling bonds of atoms of materials included in the insulating layer are terminated on its surface, and therefore a certain time period is required before the formation of the critical nuclei starts on the surface of the insulating layer. However, silicon atoms having dangling bonds are exposed on the surface of a silicon layer, and thus epitaxial growth of an Si film or an SiGe film starts at around the same time when the source gas is started to be supplied. Accordingly, the latent time can be counted as zero.
Meanwhile, in an SiGe-HBT, the thickness of an Si/SiGe layer 107 should be determined at a certain value in view of device design (i.e., electric properties that are intended to be achieved), and thus an Si/SiGe layer 107 having a greater thickness than the value can not be formed. Moreover, it is well known that use of an SiGe epitaxial film with a greater Ge content is advantageous to improvement of the high-frequency properties of the SiGe-HBT. Specifically, the growth rate of the SiGe epitaxial film increases with the increasing Ge content of SiGe. Thus, epitaxial growth of a single crystalline SiGe film tends to be completed in a shorter time, whereas the latent time before the formation of growth nuclei for epitaxial growth of a polycrystalline SiGe film tends to become longer. This is probably the reason that, in the SiGe-HBT including a base layer with a high Ge content, i.e., an about 11% Ge content (on average), only an island-shaped SiGe polycrystals have been grown as shown in FIG. 17A.
As has been described, it has been found that in the SiGe-HBT, it is basically difficult to form a polycrystalline film having a sufficient thickness on an insulating layer by non-selective epitaxial growth since epitaxial growth of an SiGe film is required to be performed under the constraint that the Si/SiGe layer 107 and the SiGe film of the Si/SiGe layer 107 should have respective predetermined thicknesses. Moreover, as the Ge content of the SiGe epitaxial film is increased for the purpose of improving electric properties of a semiconductor device such as the SiGe-HBT, it becomes more difficult to form a polycrystalline film.
Furthermore, the polycrystalline film formed on the surface of the insulating layer is to serve as a underlying layer in a subsequent process step. Therefore, the polycrystalline film should have a fine surface morphology so that lithograpy and dry-etching processes can be stably performed.
For details of the relation between Ge content and selectivity, refer to, for example, the following paper: K. Aketagawa Jpn J. Appl. Phys. Vol. 31 (1992) pp. 1432-1435, xe2x80x9cSelective Epitaxial Growth of Si and Sil-xGex Films by Ultrahigh-Vacuum Chemical Vapor Deposition Using Si2H6 and GeH4xe2x80x9d.
An object of the present invention is to provide, by taking measures for improving non-selectivity of SiGe epitaxial growth, a semiconductor device, such as an SiGe-HBT, that allows the formation of a polycrystalline film having a sufficient thickness on the surface of an insulating layer currently with the formation of a single crystalline epitaxial layer on the surface of a single crystalline semiconductor layer while fully maintaining its properties as designed, and a method for fabricating the same.
A semiconductor device according to the present invention includes: a single crystalline underlying layer formed in part of a substrate; an insulating layer formed in another part of the substrate; a semiconductor layer epitaxially grown above the underlying layer and having a composition represented by Si1-x1-y1Gex1Cy1 (where 0 less than x1 less than 1, 0xe2x89xa6y1 less than 1); a buffer layer epitaxially grown between the underlying layer and the semiconductor layer and having a composition represented by Si1-x2-y2Gex2Cy2 (where 0xe2x89xa6x2 less than 1, 0xe2x89xa6y2 less than 1, 1-x2-y2 greater than 1-x1-y1); and a polycrystalline semiconductor layer formed on the insulating layer and including a semiconductor having substantially the same composition as the buffer layer and a semiconductor having substantially the same composition as the semiconductor layer.
According to this structure, the buffer layer having a greater Si content than the semiconductor layer is provided between the underlying layer and the semiconductor layer and the polycrystalline semiconductor layer formed on the insulating layer includes a semiconductor having substantially the same composition as the buffer layer. Accordingly, non-selectivity can be improved and thus a polycrystalline layer having a relatively great thickness can be obtained.
The single crystalline underlying layer is preferably a silicon layer.
The semiconductor layer is an SiGe layer or an SiGeC layer, the buffer layer is a silicon layer and the polycrystalline semiconductor layer contains at least SiGe. Accordingly, a polycrystalline layer including polycrystalline SiGe having a small resistance can be obtained.
A semiconductor device in which the underlying layer is a collector layer, the semiconductor layer has at least part serving as a base layer and the polycrystalline semiconductor layer serves as at least part of a base lead-electrode and which functions as a heterojunction bipolar transistor can be also obtained.
A semiconductor in which the polycrystalline semiconductor layer serves as at least part of an MIS transistor and which functions as a BiCMOS device can be formed.
The buffer layer preferably has a thickness of not less than 2 nm nor more than 20 nm.
A method for fabricating a semiconductor device according to the present invention includes the steps of: (a) pre-cleaning a substrate including a single crystalline underlying layer having a composition represented by Si1-x3-y3Gex3Cy3 (where 0xe2x89xa6x3 less than 1, 0xe2x89xa6y3 less than 1) and an insulating layer; (b) forming, after the step (a), a buffer layer having a composition represented by Si1-x2-y2Gex2Cy2 (where 0xe2x89xa6x2 less than 1, 0xe2x89xa6y2 less than 1) on the underlying layer while depositing a first polycrystalline semiconductor layer having substantially the same composition as the buffer layer on the insulating layer; and (c) forming, after the step (b), a semiconductor layer having a composition represented by Si1-x1-y1Gex1Cy1 (where 0 less than x1 less than 1, 0xe2x89xa6y1 less than 1) on the buffer layer while depositing over the insulating layer a second polycrystalline semiconductor layer having substantially the same composition as the semiconductor layer so that the second polycrystalline semiconductor layer covers the first polycrystalline semiconductor layer, wherein a relation represented by the inequality of 1-x2-y2 greater than 1-x1-y1 holds between both the compositions of the semiconductor layer and the buffer layer.
According to the method, since the buffer layer has a relatively great Si content in the step (b), a time which it takes to perform the step (b) is relatively long. Accordingly, during the step (b), formation of the first polycrystalline layer in the form of islands or a continuous film on the insulating layer is ensured. Then, in the step (c), the first polycrystalline layer promotes formation of a second polycrystalline layer, so that the first and second polycrystalline layers having a great thickness as a whole can be achieved. That is to say, non-selectivity for epitaxial growth in the step (c) can be improved.
In the step (b), the first polycrystalline semiconductor is preferably formed as substantially a continuous film.
The temperature of the substrate is preferably lower when the step (b) is performed than that when the step (c) is performed. In this case, a longer time taken to perform the step (b) can be ensured as compared to the case where the substrate has a high temperature when the step (b) is performed, if the buffer layer is intended to be deposited to the same thickness in both cases. Accordingly, formation of the first polycrystalline semiconductor layer on the insulating layer can be ensured.
The difference between the substrate temperatures in the steps (b) and (c) is preferably within the range from 10xc2x0 C. to 100xc2x0 C.
In the step (a), the substrate is held at a high temperature and then the substrate temperature is reduced to a level where the step (b) is performed, and nuclei for epitaxial growth of the first or second polycrystalline semiconductor layer to be performed in the step (c) are formed on the insulating layer at a time point during the temperature reduction in the step (a). Accordingly, nuclei can be actively formed on the surface of the insulating layer, thus improving non-selectivity for epitaxial growth in the step (c) that is to be subsequently performed.
The semiconductor layer is preferably an SiGe layer or an SiGeC layer and the buffer layer is preferably a silicon layer.
By forming a semiconductor device in which the underlying layer is a collector layer, the semiconductor layer has at least part serving as a base layer and the first and second polycrystalline semiconductor layers serve as at least parts of a base lead-electrode, and which the semiconductor device functions as a heterojunction bipolar transistor, a heterojunction bipolar transistor in which a base resistance is small can be formed.
A semiconductor device in which the first and second polycrystalline layers serve at least parts of an MIS transistor and which functions as a BiCMOS device can be also formed.
The steps (b) and (c) are preferably performed under ultra high vacuum.
The temperature of the substrate is preferably in the range from 400xc2x0 C. to 650xc2x0 C. when the steps (b) and (c) are preferably performed.